One activation row (3- or 4-bit, the stored width): QuantizedLinear's bits (MLX's one-row quantized matmul), each threadgroup computing its activation chunks once (M1 Max).
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One activation row (3- or 4-bit, the stored width): QuantizedLinear's bits (MLX's one-row quantized matmul), each threadgroup computing its activation chunks once (M1 Max).