Any number of activation rows, in blocks of 8 (3- or 4-bit, the stored width), on the simdgroup matrix unit, output tiles sharing each activation fragment and K split across the threadgroup (M1 Max); the launch follows the output width.
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Any number of activation rows, in blocks of 8 (3- or 4-bit, the stored width), on the simdgroup matrix unit, output tiles sharing each activation fragment and K split across the threadgroup (M1 Max); the launch follows the output width.