1..4 activation rows; gate and up at different widths. tail is the SwiGLU arithmetic the kernel reproduces
("split": MLX's compiled swiglu over the two bf16 projections, bit for bit; "fused": the float32 sigmoid of the
same-width kernel). The exact-bits decoder at one row where the gate's GPU family qualifies it.
1..4 activation rows; gate and up at different widths.
tailis the SwiGLU arithmetic the kernel reproduces ("split": MLX's compiled swiglu over the two bf16 projections, bit for bit;"fused": the float32 sigmoid of the same-width kernel). The exact-bits decoder at one row where the gate's GPU family qualifies it.