What the Trellis kernels take from the GPU family, as explicit arguments. The single-row representations were measured on the Qwen MLP geometry (bf16, variant 13); each keeps output bits and is a speed choice.
Threadgroup codebook in the same-width gate/up decode.
Exact float32 bits in the mixed-width gate/up decoder.
The bundled runtime reduces M=5..15 matmuls with GemvWide on this GPU, so wide prefill matches it there and tiled prefill steps aside.
What the Trellis kernels take from the GPU family, as explicit arguments. The single-row representations were measured on the Qwen MLP geometry (bf16, variant 13); each keeps output bits and is a speed choice.